apollo lab notebook — limit sweeps
five experiments: thermal, power, curve optimizer, boost ceiling, and their 3⁴ factorial

The limit is the machine

Zen 4 boosts until it touches its thermal limit and holds there. Every run rode its programmed ceiling within 1 °C for the full window — the runtime SMU write (RSMU SetTctlMax 0x59) behaves identically to the BIOS setting.

What each degree buys

Renders per hour climbs fast then flattens: over 60% of the total gain arrives in the first ten degrees. Power keeps climbing linearly the whole way — 85 → 95 °C costs another 17 W for 2.1% more work.

Efficiency

Renders per hour per watt. The 70 °C setting is the thermal sweep's efficiency ceiling; 95 °C (stock) does the most work and wastes the most doing it. 80 °C is the balanced pick — most of the speed, modest heat.

Data

Governor handoff

With the thermal limit pinned at 80 °C, the power cap rules until the chip naturally draws more than the cooler can shed at 80 °. Points up to 105 W run below the thermal ceiling (temps 54–76 °C); at 120 W and 140 W the chip hits 80 ° drawing an identical ~116 W at identical ~4645 MHz — the thermal limit has taken over and extra PPT headroom buys nothing.

What each watt buys

A far steeper lever than temperature: 60 → 120 W is +62% throughput. Efficiency peaks at 75 W (1.29 r/hr/W), not at the bottom — below that the IO die's fixed ~15–20 W overhead eats a growing share of the budget, so starving the cores harder loses efficiency. 75 W keeps 80% of max throughput at 66% of the power.

Data

120 W vs 140 W score difference is run-to-run noise, not signal: same power, same clocks, both thermally bound (the thermal sweep's 80 °C point landed between them at 29.31 s). Drift check 46.69 → 46.44 s = 0.5%, pass.

Undervolt as a performance knob

All-core CO margin swept −20 → +20 at an operating point where both limits bind at once (~114 W at 80 °C), so every millivolt saved converts to clocks. Clocks fall perfectly monotonically with margin — ~85 MHz per 10 CO steps at constant power. The daily-driver −20 is worth ~1.5% over CO 0 and ~5–8% over +20; −10 vs −20 is a statistical tie in throughput.

Data — with a caveat

Drift check failed: the closing −20 repeat ran 3.3% faster than the opening −20 (27.22 vs 28.16 s), past the 2% tolerance — falling evening ambient gave later points a tailwind. The trend direction is solid (clocks are monotonic at constant watts), but the +20 penalty is likely understated. Bonus finding from the pre-sweep readback: the SMU reports margins for all 16 core slots, and exactly two per CCD read +0 — those are the fused-off cores of the 2×6-from-2×8 die, not a misapplied BIOS setting. All 12 live cores confirm −20.

The cooler sets the real ceiling

Boost clock ceiling swept at open limits so the cap alone governs. Two discoveries: the SMU refuses ceilings below base clock (4700 MHz — writes clamp on readback), and only the 4700 point actually binds. From 5000 MHz up the chip thermally saturates at 95 °C / ~141 W with all-core clocks topping out at ~4.9 GHz — ceilings above that are decorative for all-core work. Pinning at base clock keeps 94% of throughput at 87% of the power, 10 °C cooler, with the tightest render-time σ of any configuration tested.

Data

Drift check 27.55 → 27.23 s = 1.2%, pass. Cross-sweep caveat: this sweep ran hours after Parts 1–3 and its unconstrained point is ~9% faster than the morning's equivalent at the same clocks and watts — compare within sweeps, not across them. Practical verdict vs the PPT knob: efficiency is a wash at matched power; a PPT cap preserves single-thread boost (better daily eco), a clock pin buys batch-time consistency.

How the knobs interact

All four knobs crossed at 3 levels each (Tctl 70/80/95 · PPT 75/105/140 W · CO −20/0/+20 · boost 4700/5200/5700), randomized order, 10 center-point anchor repeats. Anchors landed within ±0.1 rph (8/10) and room temperature held 29.4–30.2 °C all night — no drift correction needed. Knob ranking by main effect: PPT (18% swing) » CO (8%) » Tctl (4.4%) » boost ceiling (<1%, statistically dead).

The governor, mapped

The Tctl × PPT cell means prove the min() structure: at 75 W the thermal column is flat to 0.1 rph (thermal limit irrelevant when power-starved); at 140 W the full 10% thermal spread appears. Binding classification across all 81 cells: 46 power-bound, 34 thermal-bound, 1 clock-bound. CO is the exception — the only knob that pays under every binding regime (+4–5 rph per 20 counts in every row of every table), because an undervolt buys clocks-per-watt no matter which budget is exhausted.

Winning configurations

Undervolt is in every winning corner. Best efficiency stacks all three tricks — power cap at the sweet spot, CO −20, clock pin — and beats the best single-knob result from Parts 1–4 (1.29 r/hr/W) by 13%.