Mapping every tuning knob on a Ryzen 9 7900X — from a running system
Modern Ryzen exposes its whole PBO2 control surface — thermal limit, power
budget, curve optimizer, boost ceiling — through the SMU's mailbox interface, and on Linux
the ryzen_smu kernel driver makes every one of them writable at runtime. No
BIOS round-trips, which means sweeps can be scripted. So: four single-knob sweeps, then an
overnight 81-run full factorial to map the interactions. The short version —
power budget dominates, the undervolt is the only free lunch, and the boost
ceiling turns out to be decorative.
apollo
- cpu
- Ryzen 9 7900X · 12c/24t Zen 4
- board
- MSI MAG X870E Tomahawk WiFi · BIOS 2.A91
- memory
- 96 GB DDR5
- gpu
- Radeon RX 7900 XT
- cooling
- AIO liquid — sustains ~4.9 GHz all-core / 141 W
- os
- CachyOS · kernel 7.1.3
- baseline
- Tctl 70 °C · CO −20 · boost +100 (BIOS)
- ambient
- ESPHome BME280 node logging the room at 0.1 Hz
Runtime knobs, scripted sweeps
Each knob maps to an RSMU mailbox command (command IDs are per-generation — these are
Zen 4 / Raphael, sourced from the ZenStates-Core project). Writes are 6×u32 args +
a command ID through /sys/kernel/ryzen_smu_drv/; values persist until reboot,
when the BIOS settings return. That makes experimentation unusually safe — a hang is
cured by the reset button.
| knob | rsmu cmd | arg | quirk found |
|---|---|---|---|
| thermal limit | 0x59 SetTctlMax | °C | — |
| power (PPT) | 0x56 SetFastLimit | mW | — |
| curve optimizer | 0x07 / 0x06 (all / per-core) | two's-compl. low 16 bits | fused-off core slots read back +0 |
| boost ceiling | 0x70 (readback 0x6E) | MHz | SMU clamps below base clock (4700) |
Benchmark: repeated Blender BMW27 CPU renders in 4–6 minute windows — cooldown to <55 °C, one discarded warmup render, then score = renders/hour. Telemetry at 1 Hz (k10temp, cpufreq, RAPL). Drift control mattered: day-time ambient swings moved scores by up to 9%, so the factorial ran overnight with randomized run order and a repeated center-point anchor every 9 runs. The anchors landed within ±0.1 renders/hour — the room, logged by the ESPHome node, held within 0.8 °C all night.
What each knob is worth
Main effects from the 81-run factorial (Tctl 70/80/95 × PPT 75/105/140 W × CO −20/0/+20 × boost 4700/5200/5700). Wider span = stronger knob.
The interaction structure is the real finding. These limits form a min() governor — the tightest constraint wins and the rest go dead. At PPT 75 W the thermal limit's effect is exactly zero (flat to 0.1 r/hr across 70/80/95 °C); at 140 W its full 10% spread appears. Of 81 cells, 46 were power-bound, 34 thermal-bound, 1 clock-bound. The curve optimizer is the lone exception: an undervolt buys clocks-per-watt under every regime, so CO −20 pays +4–5 r/hr in every row of every table.
The efficiency frontier
All 81 configurations, throughput vs measured package power, colored by which limit was actually governing. The frontier climbs steeply to ~118 W and then flattens hard — and 19 of its 20 points carry the −20 undervolt.
Pick by goal
Measured cells, not extrapolations. Every recommendation keeps CO −20.
# outright top performance
# daily-fast — the knee
# current daily (reference)
# maximum efficiency
Six numbers that summarize the day
| finding | number | consequence |
|---|---|---|
| knob ranking (all-core) | PPT 18% ≫ CO 8% ≫ Tctl 4.4% ≫ boost <1% | tune power first; ignore boost ceiling |
| min() governor | thermal effect = 0.0 r/hr at 75 W | a knob only matters where it binds |
| undervolt | +4–5 r/hr in every regime | keep CO −20 in every profile |
| cooler ceiling | ~4.9 GHz all-core / 141 W @ 95 °C | more speed needs better cooling, not settings |
| efficiency peak | 75 W PPT | eco profiles shouldn't go lower |
| ambient sensitivity | 9% day swing · ±0.1 r/hr overnight | benchmark overnight; log the room |
Further experiments
Per-core curve optimizer
The all-core −20 is limited by the weakest of 12 cores; the best cores usually take −30/−40. Tooling already supports per-core writes — the cost is the stability soak (hours of pinned per-core stress). Expected +1–3% on top of every profile.
GPU: RX 7900 XT
amdgpu exposes both a power cap (power1_cap) and clock/voltage offsets
(pp_od_clk_voltage) at runtime — the same sweep methodology transfers
directly. A 315 W GPU likely hides an eco plateau at least as large as the CPU's.
Cooling as the fifth knob
Pump and case fans ran mid-curve all day. PWM sweeps would measure how far the thermal-bound ceiling (4.9 GHz / 141 W) moves per decibel — the same map, approached from the dissipation side.
Workload generalization
Everything above is all-core FP rendering. Re-running the four recommended points under 7-Zip and a kernel compile should shrink PPT's dominance and surface memory sensitivity — one evening of machine time.
Memory / fabric
FCLK, UCLK and DDR5 timings have no runtime path, so those are reboot-per-point sweeps — worth designing only after the workload study says memory matters.
Static overclocking
The SMU's OC-mode commands are mapped, but fixed voltage plus disabled boost safeties buys little on a chip whose cooler saturates at 4.9 GHz. Documented, not recommended.